1. Field of the Invention
The present invention relates generally to semiconductor devices utilizing a plurality of internal power supply voltages at different levels and particularly to semiconductor devices and level conversion circuits having a function of converting a level of an internal signal. More specifically, the present invention relates to configurations for providing a reduced current consumption and preventing an erroneous circuit operation in a certain mode of operation such as a data holding mode.
2. Description of the Background Art
In a boundary region between circuits operating with supply voltages at different levels, a level conversion circuit is generally used to accurately turn on and off a transistor. In a MOS circuit with a MOS transistor (an insulated gate field effect transistor) being a component, in particular, such a level conversion circuit is used in a region transferring a signal from a circuit using a lower voltage as an operating power supply voltage to a circuit using a higher voltage as an operating power supply voltage, so as to set a gate-source voltage of the MOS transistor accurately to or below its threshold voltage.
This level conversion circuit converts a signal having a first logic level of a first power supply voltage level to a signal having the first logic level of a second power supply voltage level higher than the first power supply voltage. Examples of such a level conversion circuit are shown in Japanese Patent Laying-Open Nos. 2001-298356 and 7-106946. These prior art documents describe as the level conversion circuits a latch-type level shift circuit, in which a configuration is shown to control turning on/off of a pull-up transistor in a level conversion portion (a latch portion) in accordance with a level-converted signal, to reduce a through current flowing upon transition of a data signal.
One such MOS circuit device utilizing internal voltages at a plurality of different voltage levels is a dynamic random access memory (DRAM). In such DRAM, a plurality of internal voltages having different voltage levels are generated from an external power supply voltage and an inputting and outputting power supply voltage for an interface portion is externally supplied. The internal voltages include an array power supply voltage Vdds supplied to a memory cell array portion, a peripheral power supply voltage Vddp supplied to peripheral circuitry, and a high voltage Vpp transmitted on a selected word line in the memory array. For example, if the external power supply voltage is 3.0V, peripheral power supply voltage Vddp is, for example, 2.5V to allow the peripheral circuitry to operate at high speed. Array power supply voltage Vdds is, for example, 2.0V to insure a dielectric breakdown of a memory cell capacitor and also to reduce an internal signal amplitude to reduce charging and discharging current at a bit line and others.
Furthermore, a selected word line is supplied with high voltage Vpp at, for example, 3.6V to ensure that data at the array power supply voltage level is written without loss of a threshold voltage of an access transistor in a memory cell and also transport electric charges rapidly between a bit line and the memory cell capacitor via the access transistor.
A processing system such as a server including such a DRAM employs a large number of semiconductor devices. Accordingly, to reduce the current consumption in an entire system, it is an important factor to reduce current consumption in the semiconductor devices. Furthermore, for applications to mobile equipment and the like, a battery is used as a power supply and to extend the life time of the battery, an internal semiconductor device is required to reduced power consumption.
When a DRAM or a similar memory is not accessed and data is simply held in the DRAM, a power down mode is normally set. In the power down mode, power supply to an input/output circuit other than a circuit receiving a command instructing an operation mode is interrupted, and internal to the DRAM a refresh operation is performed at prescribed periods to hold data.
To furthermore reduce power consumption, a deep power down mode is set to stop generation of internal power supply voltage. In the deep power down mode, if generation of peripheral power supply voltage Vddp is stopped, a control circuit receiving the peripheral power supply voltage as an operating power supply voltage to generate an internal control signal outputs a control signal having an uncertain voltage level. If such control signal is used to control an operation of a circuit generating the high voltage Vpp, a level conversion circuit is employed for converting a signal having an amplitude of the peripheral power supply voltage Vddp level to a signal having an amplitude of the high voltage Vpp level. For a circuit generating a control signal of the external power supply voltage Vddq level from a signal of the peripheral power supply voltage Vddp level, similarly a level conversion circuit is employed.
For such level conversion circuit, a latch-type shift circuit is typically used, as described previously. If an input signal to such latch-type level shift circuit has an uncertain voltage level to have the voltage level electrically floated up, a through current flows via one of cross-coupled P-channel MOS transistors through a MOS transistor receiving this uncertain signal. Thus, in this level conversion circuit portion in the deep power down mode, a signal in the uncertain state causes a through current to flow and current consumption cannot be reduced. Furthermore, such a through current may cause a latch state to be inverted and a circuit at a subsequent stage may erroneously operate.
In the level shift circuits described in the above described prior art documents, a through current flowing upon signal transition is reduced by feeding back a level-converted signal to cut off a path passing the through current upon the signal transition. However, with this configuration, if in the deep power down mode, the power supply to the circuit generating an input signal is stopped and the input signal enters an uncertain state, the input signal may electrically float up in voltage level to form a path causing a through current flow, resulting in disadvantageously increased power consumption.
The prior art documents intends to simply reduce a through current flowing upon signal transition to reduce the power consumption and to change a signal at high speed to perform a level conversion operation. These documents, however, fail to give any consideration to a disadvantageous through current in an operation mode, such as the deep power down mode, in which supply of a power supply voltage to a circuit supplying an input signal is stopped.